1. Field of the Invention
The invention relates to static semiconductor read only memories, and in particular memory circuits composed of field effect transistors of either the depletion mode or enhancement mode selected depending upon the information to be stored therein.
2. Prior Art
Various types of semiconductor read only memories (ROMs) are known in the prior art. U.S. Pat. No. 4,074,238 describes a read only memory including a plurality of memory circuits connected in parallel with one another across a first line and a second line. In each of such memory circuits a first insulated gate field effect transistor (FET) of either the depletion type or the enhancement type is provided. The type of each FET is individually selected depending upon the particular information bit to be stored in that bit cell. The FETs are connected in series with a second insulated gate FET of enhancement type. Such a construction enables a ROM to be implemented by merely modifying the mask pattern for forming the FETs in the circuit.
Another implementation of a ROM using enhancement and depletion type FETs is shown in U.S. Pat. No. 4,142,176. In such patent the ROM is structured as a series structure (NAND logic), with the transistors arranged in an array of input rows and output columns.
Logic programming of the matrix may be realized by providing predetermined ones of the MOS elements of the matrix with structurally differentiated portions with respect to the remaining elements. The transistors of the matrix may be identified as elements of first and second sets, the elements of each set including structurally differentiated portions which provide first and second modes of operation, respectively. For example, the elements of the first set may have structurally differentiated portions relative to the elements of the second set which permit operation of the transistors of the first set in the first mode in which current is conducted through source and drain portions in response to a first applied gate potential corresponding to a first logic state, (for example V.sub.D volts for a logic "1" for N-channel enhancement mode MOSFET devices), and in which the flow of current through the source and drain is prevented in response to a second applied gate potential corresponding to a second logic state, (for example zero gate bias for a logic "0"). The elements of the second set may have structurally differentiated portions which permit operation of the elements of the second set in the second mode wherein a conductive path through source and drain portions exists without regard to the logic state corresponding to the applied gate potential, (for example, depletion mode MOSFET devices).
Such an arrangement is disadvantageous because of the apparent requirement that a precharge signal be applied for high speed operation with relatively large voltage swings to the NAND gate for suitable operation. The latter requirements means that external clock signals must be applied to the integrated circuit for operation, i.e., the circuit is a "dynamic" one with relatively large voltage swings. There are many circuit designs and applications for ROMs which are purely static, i.e. dynamic circuits are not used, and therefore such prior are dynamic ROMs could not be used in such applications.